FIG. 1 shows the block diagram of a SAR (Successive Approximation Register) ADC with the elements of Track/Hold, Comparator, N-bit DAC and Binary Search Logic. The analog input voltage (VIN) is sampled and held by Track/Hold. The Binary Search Logic is initially set to midscale (100 . . . 00). This forces the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage of ADC. The Comparator compares VIN and VDAC and determines the next operation. If VIN is greater than VDAC, the comparator output is logic high and the MSB of N-bit register remains at 1. Conversely, if VIN is less than VDAC, the comparator output is logic low and the MSB is cleared to logic 0. This binary-search algorithm continues till LSB. The conversion is complete once LSB output is obtained.
The N-bit DAC can be implemented using current, resistor or capacitor. Capacitive DAC is commonly used because capacitive DAC provides an inherent track/hold function. A capacitive DAC consists of an array of N capacitors with binary or non-binary weighted values. Capacitive DAC employs the principle of charge redistribution to generate an analog output voltage.
FIG. 2 shows an example of a 14-bit capacitive binary weighted DAC and comparator in SAR ADC. During the acquisition phase, the common terminal is connected to AC ground and all the switches are connected to the input VIN. After acquisition, the common terminal is disconnected from AC ground and all the switches connected to VIN are open. The VIN voltage is effectively sampled and stored on the capacitors. As the first step of binary-search algorithm, the bottom plate of MSB capacitor is connected to reference voltage VREF. This drives the common terminal in the positive direction by an amount equal to ½VREF. The comparator will make a decision depending on VIN is greater or less than ½VREF. As the binary-search algorithm continues, the next smaller capacitor is connected to VREF. This drives the common terminal by an amount of ¼VREF. The binary-search algorithm continues until all the DAC capacitors are exercised. The relationship of VIN and ADC digital output is described in the following equation:
      V    IN    =            B      ⁢                          ⁢      13      *                        V          REF                2              +          B      ⁢                          ⁢      12      *                        V          REF                4              +    …    +          B      ⁢                          ⁢      1      *                        V          REF                8192              +          B      ⁢                          ⁢      0      *                        V          REF                16384            VIN is the ADC input voltageB[13:0] is ADC outputsVREF is ADC reference voltage
And the time required for N-bit SAR ADC to complete one conversion is:Ttotal=Tsample+N*Tbit-test TSample is the time needed for track/holdTbit-test is the time needed for each bit-testFor conventional synchronous SARADC, each bit-test takes one clock cycle to finish. If track/hold takes M clock cycles to sample the input, then the total time of one conversion is M+N clock cycles. The relationship of ADC conversion rate and input clock rate can be described in the following equation:
      ADC    ⁢                  ⁢    Conversion    ⁢                  ⁢    Rate    =            Clock      ⁢                          ⁢      Rate              (              M        +        N            )      For example, for 14-bit SAR ADC, if track/hold sample time needs 6 clock cycles, then 6+14=20 clock cycles is needed to finish one conversion. The input clock rate needs to be 2 GHz to obtain 100 MHz conversion rate. Such high frequency clock is usually not available in the system. For System-on-Chip (SoC), it is very desirable to obtain the same frequency conversion rate as other ADC architectures like Flash ADC or Pipelined ADC. Two developed methods will be presented below to enable high conversion rate SAR ADC and eliminate the requirement of high frequency clock input of SAR ADC.